Research at Leeds Beckett
Dr Mario Marino
Dr Mario Marino
Senior Lecturer
School Of Built Environment, Engineering And Computing
0113 81 21992 M.D.Marino@leedsbeckett.ac.ukAbout Dr Mario Marino
Mario Donato Marino is currently a Senior Lecturer at Leeds Beckett University. He is currently teaching computer-systems-related courses at the School of Computing, Creative Technologies & Engineering.
Mario's current research is in computer architecture area. Mario's current work includes the design and evaluation of performance and power benefits of future and current memory systems in typical and embedded microprocessors.
Mario is mainly working to approach the challenges of future memory systems, which consist in bandwidth, latency, and energy utilization. Mario is currently participating on the reviewer board of international journals (Inderscience IJES and IJHPCN) and conferences (3PGCIC-2016, EUC 2017, ICACOMIT2016 and EMSA-2017).
Current Teaching
- Computer Systems Architecture
- Fundamentals of Operating Systems
- Operating Systems and Practice
- Msc Team Project
Research Interests
Mario's research is focused on mechanisms for improving bandwidth and latency of memory systems. Mario has started this research by proposing radio-frequency (RF) memory organizations which allows the exploration of a larger number of memory controllers in order to increase bandwidth. In future plans, Mario is likely to approach other technologies such as optical or 3D-stacking.
One of the consequences of scaling memory controllers is the reduction of the amount of memory traffic per memory controller, and reduction of the transaction queue utilization. Currently, Mario is investigating the impact of shallower transaction queues in terms of performance and energy implications.
Selected Publications
Journal articles (8)
- Marino MD (2018), Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability
https://doi.org/10.1109/TVLSI.2018.2821004
View Repository Record - Marino MD; Weng TH; Li KC (2018), Exploiting Dynamic Transaction Queue Size in Scalable Memory Systems
https://doi.org/10.1007/s00500-016-2470-x
View Repository Record - Marino MD (2018), RAMON: Region Aware Memory Controller
https://doi.org/10.1109/TVLSI.2018.2789520
View Repository Record - Marino MD; Li KC (2017), System Implications of LLC MSHRs in Scalable Memory Systems
https://doi.org/10.1016/j.micpro.2016.12.007
View Repository Record - Marino MD (2016), ABaT-FS: Towards adjustable bandwidth and temperature via frequency scaling in scalable memory systems
https://doi.org/10.1016/j.micpro.2016.06.013 - Marino MD; Li KC (2016), Implications of Shallower Memory Controller Transaction Queues in Scalable Memory Systems
https://doi.org/10.1007/s11227-015-1485-x
View Repository Record - Marino MD; Li KC (2016), Last Level Cache Size Heterogeneity in Embedded Systems
https://doi.org/10.1007/s11227-015-1576-8
View Repository Record - Marino MD; Li KC (2014), Insights on Memory Controller Scaling for Multicore Embedded Systems
https://doi.org/10.1504/IJES.2014.065000
View Repository Record
Conference contributions (1)
- Marino MD; Li KC (2015) Reducing Memory Controller Transaction Queue Size in Scalable Memory Systems Jenju, Korea 01/03/2015.
View Repository Record
Conference proceedings (peer reviewed) (7)
- Marino MD (2013) RFiof: An RF Approach to I/O-pin and Memory Controller Scalability for Off-chip Memories. In: Computing Frontiers 2013 Ischia, Italy 14/05/2013 00:00:00. : , pp. .
https://doi.org/10.1145/2482767.2482803
View Repository Record - Marino MD (2012) On-Package Scalability of RF and Inductive Memory Controllers. In: 2012 15th Euromicro Conference on Digital System Design (DSD) 05/09/2012 00:00:00. : IEEE, pp. .
https://doi.org/10.1109/dsd.2012.95 - Marino MD (2012) RFiop: RF-memory path to address on-package I/O pad and memory controller scalability. In: 2012 IEEE 30th International Conference on Computer Design (ICCD 2012) 30/09/2012 00:00:00. : IEEE, pp. .
https://doi.org/10.1109/iccd.2012.6378638 - Scoton F; Kobayashi J; Marino MD (2012) Adapted discrete-based entropy cache replacement algorithm. In: 2012 International Conference on High Performance Computing & Simulation (HPCS) 02/07/2012 00:00:00. : IEEE, pp. .
https://doi.org/10.1109/hpcsim.2012.6266969 - Gebhart M; Maher B; Koons C; Diammond J; Grattz P; Marino MD; Ranganathan N; Behnam R; Smith A; Burril J (2009) An evaluation of the TRIPS computer system. In: 14th international conference on Architectural support for programming languages and operating systems (ASPLOS) Pittsburgh 09/03/2009 00:00:00. : Association for Computing Machinery, pp. 1-12.
https://doi.org/10.1145/1508244.1508246
View Repository Record - Marino MD; Marino MD; Paulo O (2006) 32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice. In: 2006 18th International Symposium on Computer Architecture and High Performance Computing 17/10/2006 00:00:00. : IEEE, pp. .
https://doi.org/10.1109/sbac-pad.2006.5 - Marino MD (2006) L2-Cache Hierarchical Organizations for Multi-core Architectures. In: . : Springer Berlin Heidelberg, pp. 74-83.
https://doi.org/10.1007/11942634_9
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