Leeds Beckett University - City Campus,
Woodhouse Lane,
LS1 3HE
Dr Mario Marino
Senior Lecturer
Mario Donato Marino is currently a Senior Lecturer at Leeds Beckett University. He is currently teaching computer-systems-related courses at the School of Computing, Creative Technologies & Engineering.
Mario's current research is in computer architecture area. Mario's current work includes the design and evaluation of performance and power benefits of future and current memory systems in typical and embedded microprocessors.
Mario is mainly working to approach the challenges of future memory systems, which consist in bandwidth, latency, and energy utilization. Mario is currently participating on the reviewer board of international journals (Inderscience IJES and IJHPCN) and conferences (3PGCIC-2016, EUC 2017, ICACOMIT2016 and EMSA-2017).
Current Teaching
- Computer Systems Architecture
- Fundamentals of Operating Systems
- Operating Systems and Practice
- Msc Team Project
Research Interests
Mario's research is focused on mechanisms for improving bandwidth and latency of memory systems. Mario has started this research by proposing radio-frequency (RF) memory organizations which allows the exploration of a larger number of memory controllers in order to increase bandwidth. In future plans, Mario is likely to approach other technologies such as optical or 3D-stacking.
One of the consequences of scaling memory controllers is the reduction of the amount of memory traffic per memory controller, and reduction of the transaction queue utilization. Currently, Mario is investigating the impact of shallower transaction queues in terms of performance and energy implications.
Selected Outputs
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Weinhardt M; Koch D; Hochberger C; Schwarz A; Amano H; Bauer L; Cardoso JMP; Chow P; Hannig F; Kenter T (2019) Preface.
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Marino MD (2013) RFiof: An RF Approach to I/O-pin and Memory Controller Scalability for Off-chip Memories. In: Computing Frontiers 2013, 14 May 2013 - 16 May 2013, Ischia, Italy.
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Marino MD (2012) On-Package Scalability of RF and Inductive Memory Controllers. In: 2012 15th Euromicro Conference on Digital System Design (DSD), 5 September 2012 - 8 September 2012. IEEE.
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Marino MD (2012) RFiop: RF-memory path to address on-package I/O pad and memory controller scalability. In: 2012 IEEE 30th International Conference on Computer Design (ICCD 2012), 30 September 2012 - 3 October 2012. IEEE.
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Scoton F; Kobayashi J; Marino MD (2012) Adapted discrete-based entropy cache replacement algorithm. In: 2012 International Conference on High Performance Computing & Simulation (HPCS), 2 July 2012 - 6 July 2012. IEEE.
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Gebhart M; Maher B; Koons C; Diammond J; Grattz P; Marino MD; Ranganathan N; Behnam R; Smith A; Burril J (2009) An evaluation of the TRIPS computer system. In: 14th international conference on Architectural support for programming languages and operating systems (ASPLOS), 9 March 2009 - 11 March 2009, Pittsburgh. Association for Computing Machinery.
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Marino MD; Marino MD; Paulo O (2006) 32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice. In: 2006 18th International Symposium on Computer Architecture and High Performance Computing, 17 October 2006 - 20 October 2006. IEEE.
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Marino MD (2006) L2-Cache Hierarchical Organizations for Multi-core Architectures. Springer Berlin Heidelberg.
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Marino MD; Li KC (2015) Reducing Memory Controller Transaction Queue Size in Scalable Memory Systems. In: World Congress on Information Technology Applications and Services - World-IT 2015 - "Advanced Mobile, Communications, Security, Multimedia, Vehicular, Cloud, IoT, and Computing, 1 March 2015, Jenju, Korea.
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Marino M (2020) Walter: Wide I/O Scaling of Number of Memory Controllers Versus Frequency and Voltage. IEEE Access, 8 pp. 193874-193889.
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Marino MD (2018) Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26 (8), pp. 1494-1507.
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Fan W; Zhang H; Li KC; Zhang S; Marino MD; Jiang H (2018) An efficient algorithm for modelling and dynamic prediction of network traffic. International Journal of Computational Science and Engineering, 16 (3),
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Marino MD (2018) RAMON: Region Aware Memory Controller. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26 (4), pp. 697-710.
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Marino MD; Weng TH; Li KC (2018) Exploiting Dynamic Transaction Queue Size in Scalable Memory Systems. Soft Computing, 22 (6), pp. 2065-2077.
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Marino MD; Li KC (2017) System Implications of LLC MSHRs in Scalable Memory Systems. Microprocessors and Microsystems, 52 pp. 355-364.
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Marino MD (2016) ABaT-FS: Towards adjustable bandwidth and temperature via frequency scaling in scalable memory systems. Microprocessors and Microsystems, 45 pp. 339-354.
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Marino MD; Li KC (2016) Implications of Shallower Memory Controller Transaction Queues in Scalable Memory Systems. Journal of Supercomputing, 72 (5), pp. 1785-1798.
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Marino MD; Li KC (2016) Last level cache size heterogeneity in embedded systems. Journal of Supercomputing
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Marino MD; Li KC (2014) Insights on Memory Controller Scaling for Multicore Embedded Systems. International Journal on Embedded Systems, 6 (4),
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Gebhart M; Maher BA; Coons KE; Diamond J; Gratz P; Marino M; Ranganathan N; Robatmili B; Smith A; Burrill J (2009) An evaluation of the TRIPS computer system. ACM SIGARCH Computer Architecture News, 37 (1), pp. 1-12.
