Dr Mario Marino, Senior Lecturer

Dr Mario Marino

Senior Lecturer

Mario's background is on computer engineering and computer science.  His focus is in the areas of computer architecture/design/organization,  especially on multicores/manycores and memory systems, aiming performance improvement on the former and bandwidth on the latter, whilst reducing power on both.

To approach the scaling of multicores in the BigData era, where bandwidth-bound programs are likely to be present in many scenarios, the contention on the memory system is very high, even using 3Dstacking memory systems (e.g. HBM).

He is working on evaluating 3Dstacking and interconnection bottlenecks aiming to improve contention/improve bandwidth due to high memory demand by multicores and manycores in the BigData and IoT eras. As an important outcome of this evaluation is to guide the application of techniques targeting data movement, aiming to find a processor-in-memory (PIM, hot area of research) organization/approach to save energy.

Mario is also very interested in the open-license RISC-V. Its open-license feature is very exciting since it opens the opportunities to advance the area of computer design using a different path from traditional industry.

Mario is very interested in working with prospective PhD/MsC/MFill students in the above related fields.

Current Teaching

  • Software-systems (ARM-embedded) (postgrad)
  • Operating systems
  • Project
  • Computer communications

Research Interests

To approach the bandwidth demands of BigData bandwidth-bound like programs  in multicores (CPUs) and manycore (GPUs) in 3DStacking, Mario is performing a design space investigation of different architectural techniques allowed by the employment of 3DStacking HBM TSVs and shorter distance optimizations, both to enable higher traffic and lower energy at the memory side. Mario is using its previous exploration experience in Wide I/O and employing gem5 simulator to perform the referred design space exploration in HBM systems. The goal is to determine the understand the saturation of these memory systems under a large number of cores/caches' generated memory requests.

In the processor-in-memory (PIM) area, he is looking at RISC-V processor (like Linux, open-license/open-source processor) and evaluating different processor and memory organizations to improve speedup/bandwidth whilst reducing energy/power. There are very open-license open-source RISC-V distributions available (BOOM, Rocket, DarkRISC, etc) and Mario is investigating some of these implementations aiming the area of embedded systems. Likely, Xilinx Vivado IDE and related boards are likely going to be employed in this investigation and compatible hardware development language to perform eventual modifications to the open-license projects.

Previous research has approached the I/O pin problem via using radio-frequency(RF) to communicate DRAM ranks with memory controllers (MCs), which can enable pin scaling, thus MC scaling. As a result, Mario has proposed the concepts of "RFpins" and "RFpads", and these enabled bandwidth gains of up to 8x for multicores and GPUs. RFpins and RFpads enabled RF-based MCs (RFMCs) compared to a traditional MC-based system.

Before that, in the area of multicores, Mario has concentrated on evaluating the effects of different LLC cache size parameters in terms of performance and energy.

Mario's postdoc research aimed to assist the TRIPS (University of Texas at Austin in-house processor) to port and optimize (assembly language) applications for this its dataflow-based architecture (pipelined 128-block instructions, where blocks are executed in dataflow-fashion).

PhD and MsC have focused on distributed virtual shared memory (DVSM) libraries which emulate a multiprocessor on a network of PCs (Linux and FreeBSD), aiming scalability (nodes or processors).

Services to the community:

  • Associated Editor on IEEE Access Journal since October 2020
  • Associated Editor on the Inderscience International Journal of Embedded Systems (IJES) since 2015
  • Program Committee (PC) member in more than 30 International Conferences and Workshops. Programme Chair in one Conference

More information can be found on Mario's website.

Dr Mario Marino, Senior Lecturer

Ask Me About

  1. Computing
  2. Creative technologies

Selected Outputs

  • Weinhardt M; Koch D; Hochberger C; Schwarz A; Amano H; Bauer L; Cardoso JMP; Chow P; Hannig F; Kenter T (2019) Preface.

  • Marino MD (2013) RFiof: An RF Approach to I/O-pin and Memory Controller Scalability for Off-chip Memories.

  • Marino MD (2012) RFiop: RF-memory path to address on-package I/O pad and memory controller scalability.

  • Marino MD (2012) On-Package Scalability of RF and Inductive Memory Controllers.

  • Scoton F; Kobayashi J; Marino MD (2012) Adapted discrete-based entropy cache replacement algorithm.

  • Gebhart M; Maher B; Koons C; Diammond J; Grattz P; Marino MD; Ranganathan N; Behnam R; Smith A; Burril J (2009) An evaluation of the TRIPS computer system.

  • Marino MD; Marino MD; Paulo O (2006) 32-core CMP with multi-sliced L2: 2 and 4 cores sharing a L2 slice.

  • Marino MD (2006) L2-Cache Hierarchical Organizations for Multi-core Architectures.